Clark School Home UMD

ISR News Story

A Dynamic Memory Allocator for Embedded Systems with Scratch-Pad Memory (ISR IP)

ISR intellectual property available to license

Inventors
Rajeev Barua, Sumesh Udayakumaran

U.S. Patent: 7,367,024

Description
Developed by University of Maryland researchers, this invention is a method of allocating program data automatically in embedded computing systems containing scratch-pad memories. Compared to currently used compiler technology for embedded systems, this new method reduces time, power consumption, programmer burden and cost.

This technology has applications as a memory allocation tool for use in a compiler and as a hardware design tool. It can improve embedded processor boards of all types, a growing and lucrative market.

Embedded computing systems are computing processors in devices other than dedicated computers. Compilers for embedded systems produce executable code for embedded processors from source-level computer programs.

The primary novelty of the invented method is that it is able to allocate all kinds of global and stack variables in programs to scratch-pad memory using a dynamic method other than software caching. A dynamic method is one where the allocation of variables in memory is allowed to change during the run of the program.

Compared to present-day hardware design tools, this technology, when used to predict the smallest size of scratch-pad memory that meets runtime requirements, can reduce the size of scratch-pad memory required, resulting in reduced hardware cost.

Compared to using hardware caches, this technology allows for better utilization of scratch-pad memories, which have inherent advantages over caches in terms of cost, power consumption and access time. This technology allows scratch-pad memories to live up to their full advantageous potential.

For more information
If you would like to license this intellectual property, have questions, would like to contact the inventors, or need more information, contact ISR External Relations Director Jeff Coriale at coriale@umd.edu or 301.405.6604.

Find more ISR IP
You can go to our main IP search page to search by research category or faculty name. Or view the entire list of available IP on our complete IP listing page.

ISR-IP-Barua ISR-IP-embedded ISR-IP-compilers

Related Articles:
Simulator of the Explicit Multi-Threading (XMT) Computer Architecture and Software Tools for Programming It (ISR IP)
Binary Rewriting Without Relocation Information (ISR IP)
Automatic Parallelization Using Binary Rewriting (ISR IP)

June 21, 2007


Prev   Next

 

 

For more information, contact ISR External Relations Director
Jeff Coriale at coriale@umd.edu or 301.405.6604.

Current Headlines

Relive Totality With Clark School Images, Videos

Researchers part of two NSF Neural & Cognitive Systems grants worth more than $1.2 million

ISR researchers win additional $948K NSF Neural and Cognitive Systems grant

Schonfeld, Ryzhov team up for NSF EAGER grant

Yu Named ASME Fellow

Khaligh-led student team wins award at IEEE IFEC competition

Former postdoc Eirini Tsiropoulou named to IEEE ComSoc "rising stars" list

TEDCO Invests $1M into Innovative Companies Including Rajeev Barua’s Startup SecondWrite LLC

Banis wins poster design award at Global Grand Challenges Summit

ISR faculty leading bio-inspired robotics and transportation electrification REUs

News Resources

Return to Newsroom

Search News

Archived News

Events Resources

Events Calendar