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Professor Alexander Barg (ECE/ISR) is the principal investigator for a new National Science Foundation Collaborative Research grant, Coding for Nano-Devices, Flash Memories, and VLSI Circuits. The three-year, $299K grant will explore applications of coding theory to digital circuit design.
Over the past 50 years, error-control coding has been employed with spectacular success by the communications and data storage industries to achieve performance trade-offs that would have been otherwise impossible. What has been recognized only recently is that coding theory could be just as useful in applications other than communications and storage.
The research will address a spectrum of technologies ranging from nanoscale circuits and memory chips to more conventional VLSI architectures. Problems in each technology are inherent to the physics of the underlying medium or system.
Barg will show that sophisticated coding—based upon methods and ideas deeply rooted in algebraic and combinatorial coding theory—offers a significant advantage that can enable circuit designers to achieve system trade-offs that would have been otherwise impossible.
Barg will develop new coding schemes for efficient addressing and correction of manufacturing defects in next-generation memory nano-devices, in particular the nano-wire crossbar. He also will come up with advanced coding techniques for high-density flash memories, based upon ground-breaking recent ideas of floating codes and rank-modulation coding. In addition, the research will develop coding schemes to reduce power dissipation and avoid cross-talk in VLSI circiuts, with particular emphasis on both on-chip and off-chip buses.
The techniques developed in a range of well-known combinatorial problems in coding theory, including covering arrays, separating codes, intersecting codes, and qualitatively independent set families will be applied to circuit design.
September 18, 2008
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