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Associate Professor Rajeev Barua (ECE/ISR) is the principal investigator for a new National Science Foundation Computer Systems Research-Embedded and Hybrid Systems (CSR-EHS) grant, "Memory Management as a Run-Time Service." The three-year award is worth $180,000.
Abstract
SRAM memories are essential to improving run-time, energy use and real-time bounds. Many embedded processors contain Scratch Pad Memory (SPM), unenhanced SRAM that is mapped to a portion of the address space. They offer better real-time guarantees than caches, an alternate SRAM memory type. Compiler methods to allocate objects automatically to SPM have existed for a decade, but a recent survey did not find even a single commercial compiler that does automatic SPM allocation. Instead, programmers manually specify the SPM allocation using annotations. Reasons may include developer unawareness of SPM, unwillingness to include another feature in the toolchain, and the expense of repeated implementation in each compiler.
This research is developing a SPM allocation strategy that is completely implemented inside a binary rewriter. This binary rewriter is called automatically by the operating system the first time the program is loaded to memory. Subsequent executions derive the benefits of SPM with no additional overhead. This approach makes SPM a run-time-provided resource for the first time, much like cache and virtual memory are, making it ubiquitous and transparent to the software toolchain. The broader impacts of the research are (i) embedded systems that achieve high speed and real-time behavior at lower cost; (ii) portable devices with lower energy use, hence longer battery life; (iii) programs that are portable to any SPM size ? an important practical advantage; (iv) an educational and outreach program including graduate student training, undergraduate and graduate courses, internships, and a workshop on memory management.
August 21, 2007
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