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Vahid Tabatabaee Detailed Resume: Word Format, PDF Format Education PhD/ Electrical Engineering, 2003 University of Maryland at College Park GPA 4.00 Advisor: Prof. Leandros Tassiulas. Dissertation: "Scheduling and Rate Provisioning for Cell Based Input-Buffered Switch Fabrics"
MSc/ Electrical Engineering, 1992 University of Tehran GPA 18.45/ 20. Ranked 1st among 20 students.
BSc/ Electrical Engineering, 1989 Sharif University of Technology GPA 16.73/ 20. Ranked 4th among 50 students. Work Experience Research Associate,
Research Associate 2003-present: University of Maryland Institute for Advanced Computer Studies. Research and Development of centralized and distributed optimization algorithms for IP traffic engineering and QoS provisioning. Formulation and algorithm development for robust routing in networks with unpredictable traffic demands.
Research Associate 2004-present: University of Maryland, Department of Computer Science. Design of parallel direct search algorithms for on-line optimization and self-tuning of complex software. Statistical modeling and analysis of performance variations in high performance computing systems. Autonomic fault diagnosis for soft-ware systems.
Principal Architect Engineer 2001- 2003, Zagros Networks, Rockville, MD Switch Fabric architecture and algorithm design. Research and Development of new algorithm for traffic scheduling in networks. Design and architect a two chip switch fabric solution that supports unicast, multicast, TDM traffic. Representative of the company in switch fabric benchmarking group of Network Processor Forum (NPF). Editor of the Fabric benchmark test suite document for NPF.
Summer Internship, Summer 1998, Lucent Technology (Yurie Systems), MD Implementation of a new standard 2400 bps vocoder. Lucent technology considered using this vocoder in their ATM aggregator switches.
Research Assistantship 1996- 2001 University of Maryland, Institute for Systems Research Working on several research problems on data networking, including. 4 years active research, review, and study of scheduling algorithms for input-buffered switches. 1 year research, and study on scheduling and multiple access control schemes for shared media channels, with applications in broadband wireless systems, cable modems and satellite systems.
Teaching Assistantship 1995-1996 University of Maryland, Department of Electrical and Computer Engineering Supervising and assisting under graduate student in DSP processor lab.
Research Engineer 1991-1995 Sharif University of Technology Working on several signal processing projects related to design of speech coders, recognizers and telecomm systems.
Patents “Method and Apparatus for Scheduling in a Packet Buffering Network”, submitted to US patent office. “Cell Sequence Number Synchronization System and Method”, submitted to US patent office.
“Method and Apparatus for Parallel Weighted Arbitration Scheduling for a Switch Fabric”, submitted to US patent office.
“Method and Apparatus for Weighted Arbitration Scheduling separately at the input ports and the output ports of a Switch Fabric”, submitted to US patent office.
“Method and Apparatus for Arbitration Scheduling with a penalty for a Switch Fabric”, submitted to US patent office.
“Hybrid Neural Network for Speech Recognition”, Patented in Iran, 1993.
Honors Editor of the switch fabric benchmarking document of the Network Processor Forum.
Received the prestigious Kharazmi Award for Design and implementation of a 2400 bps Voice-Data-Fax Communication System, 1994.
Ranked 1st. among the graduate students of Elec. Eng. Dept. 1992.
Ranked 3rd. in the university entrance exam for M.S. program among 600 students, 1989. |