PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS '04), MAY 23-26, 2004
A LOW-POWER CMOS NEURAL AMPLIFIER WITH AMPLITUDE MEASUREMENTS FOR SPIKE SORTING
HORIUCHI, T., SWINDELL, T., SANDER, D., ABSHIRE, P.
Integrated, low-power, low-noise CMOS neural amplifiers have recently grown in importance as large microelectrode arrays have begun to be practical. With an eye to a future where thousands of signals must be transmitted over a limited bandwidth link or be processed in situ, we are developing low-power neural amplifiers with integrated pre-filtering and measurements of the spike signal to facilitate spike-sorting and data reduction prior to transmission to a data-acquisition system. We have fabricated a prototype circuit in a commercially-available 1.5µm, 2-metal, 2-poly CMOS process that occupies approximately 91,000 square µm. We report circuit characteristics for a 1.5V power supply, suitable for single cell battery operation. In one specific configuration, the circuit band-pass filters the incoming signal from 22Hz to 6.7kHz while providing a gain of 42.5dB. With an amplifier power consumption of 0.8 µW, the rms input-referred noise is 20.6µV.
Keywords: neural amplifier; spike sorting
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