Adaptive Circuits
Overview |
AFGC |
AFGQ |
Adaptive Floating Gate Imager |
Adaptive Filter |
Random Number Generator
Overview
We have developed new methods for incorporating adaptation into ordinary circuits and systems in order to
overcome performance limitations due to variability in hardware (i.e., component mismatch) and task
requirements (i.e., changes in the signals or environment) to achieve high-performance, high-quality results.
The unique aspect that distinguishes this work is that these architectures that are able to adapt autonomously,
without the need for outside intervention and tweaking from outside observers or components
[J13,
J11,
J8,
J7,
J6,
C36,
C24,
C23,
C20,
C17,
C16,
C9,
C8].
We have applied these novel techniques to several classes of integrated circuits. We demonstrated that we
are able to trim CMOS comparator offset to a precision of 0.7mV
[J7,
J6,
C16,
C8],
reduce CMOS image sensor fixed-pattern noise power by a factor of 100
[J11,
C17],
adapt gain and bandwidth in analog adaptive filters to track reference signals
[J13,
C23,
C9],
and achieve 5.7 effective number of bits (ENOB) in a 6-bit flash analog-to-digital converter (ADC) operating
at 750MHz
[C36].
The adaptive circuits generally exhibit special features in addition to improved performance. These special
features provide capabilities beyond that of traditional CMOS design approaches, and they open exciting
opportunities in novel circuit designs. Specifically, the adaptive comparator has the ability to store an
accurate arbitrary offset, the image sensor can memorize previously captured scenes like a human retina, and
the ADC can adapt to the incoming analog signal distribution and perform an efficient signal conversion that
minimizes distortion and maximizes output entropy. The adaptive comparator can further be configured to
generate high quality random numbers by amplifying the inherent noise present in CMOS devices
[J8].
The Adaptive Floating Gate Comparator (AFGC)
The Adaptive Floating Gate Comparator (AFGC) is a simple 5-transistor CMOS comparator that compares differential
analog signals supplied at the input in 5 nanoseconds. It is capable of precise programming of the offset
voltage. The user supplies the desired offset at the input and .trains. the comparator using a high voltage on the
power supply Vdd. The high source-to-drain voltage on the pFET differential pair creates high-energy electrons by
impact-ionization, and these electrons are directed onto the floating gate through the conduction band of the oxide
(i.e., hot-electron injection). The threshold, and thus the comparator offset, shifts as charge accumulates on the
floating gate
[J7,
J6,
C16,
C8].
This technique has also been applied at high speed, resulting in a comparator that operates at 1.2GHz with an
offset of 199uV, or equivalently, 13 effective number of bits (ENOB) (see
[C16]).
The inverting nature of a transistor is utilized in pFET hot-electron-injection, so that the output signal of
the comparator forms a stable negative feedback loop for the adaptation, enabling automatic and accurate
adaptation results. The in-circuit, on-line learning feature is very attractive to reprogrammable mixed-signal
circuit (see the adaptive ADC below).
The Adaptive Floating Gate Quantizer (AFGQ)
The Adaptive Floating Gate Comparator (AFGC) is a 750MS/s 6-bit flash ADC comprising an array of 63 high
speed adaptive floating gate comparators (AFGCs)
[C36,
C16].
The on-line learning feature of the AFGC enables manual and automatic in-circuit programming of reference
levels, eliminating both resistor ladders and comparator offset problems. Measured INL and DNL were 0.24LSB
and 0.79LSB, respectively. Standard FFT based single tone analysis gives 5.7 effective number of bits (ENOB)
and 5.3 ENOB at input frequencies of 200MHz and 387MHz, respectively.
When adaptation is turned on during operation, the ADC learns the input signal distribution and adjusts
comparator reference levels such that the ADC converts frequent signal regions with finer detail and greater
sensitivity, resulting in an overall lower distortion and higher output entropy.
The Adaptive Floating Gate Imager
Floating gate pFET injection was also designed into the pixels of a wide dynamic range image sensor
[J11,
C17].
The imager operates in the MOSFET subthreshold region, converting incident light intensity into voltage
logarithmically, with 100mV per decade intensity. Thus, the imager is extremely sensitive to the normal
mismatch levels (10mV) present in CMOS. The imager suppresses this mismatch by performing adaptation
independently and simultaneously in each pixel. The user simply supplies a uniform scene and turns on
adaptation for a few seconds, and the imager automatically compensates for fixed-pattern noise (power
reduced by 100X!). The adaptation also compensates for distortions in the light path such as the vignetting
effects commonly found in optical lenses.
If the user supplies a patterned scene rather than a uniform scene during adaptation, the inverse of the
pattern is imprinted into the floating gate memory and appears in subsequent captured images. This type of
adaptation is inherent to human vision and is commonly referred to as an "afterimage."
Adaptive Filter
We also demonstrated adaptive log domain filters with integrated learning rules for model reference estimation
[J13,
C23,
C9].
The system was implemented using multiple input floating gate transistors operating in subthreshold to
realize on-line learning of system parameters. Adaptive dynamical system theory is used to derive robust
control laws for parameter adaptation in a system identification task. Learning rules are implemented
using multiple input translinear element (MITE) structures, highlighting the elegance and symbiotic
nature of the design methodology.
