Brainstem and midbrain processing ``cells'' including the duration cell, the onset cell, highlight cell, and the coincidence-detector cell developed in Thrust area I(B) will also be implemented using VLSI techniques. We have already formulated each cell type in terms of signal processing constructs (i.e. filters, delays, nonlinearities). Therefore, the DSP chip approach is an obvious one, although possibly cumbersome due to the fanout structure of the overall model, which entails multiple temporal channels per each of many (>100) frequency channels. The VLSI approach is a natural for such a design in which parameterized cells may be repeated with a high redundancy factor. We have already in hand the CMOS cells that correspond to the signal-processing formulation of each ``cell'' type.