This proposed project concerns the implementation of cortical multiscale processing discussed in detail in Thrust areas I and II earlier. Recall that this model analyzes the acoustic input into three independent dimensions: a logarithmic frequency axis, a local symmetry axis, and a local spectral bandwidth. The VLSI cochlear models discussed above perform the early logarithmic frequency analysis, and can thus be used as a ``front end'' to this VLSI AI model. But appropriate symmetry and bandwidth filters need to be developed to fully implement such a model. The need to pack three dimensions of analysis into a two-dimensional microchip suggests the requirement that the solution must be exceedingly efficient in terms of space and power. We have therefore decided to look to circuits based on subthreshold analog processing to achieve the desired filter circuits. Specifically, we propose to investigate the use of asymmetric resistive networks (commonly used in retinal filtering implementations) to implement the asymmetric AI receptive fields. An alternate approach that we also plan to study is the use of resistive networks with nearest, second nearest, and perhaps even third nearest neighbor connections. These networks have already been used successfully to develop higher-order IIR spatial filters. Finally, we shall need to determine the best mechanism to interface the AI model with test equipment and other signal processing systems. The ``event-address protocol'' worked on by the ETH/UZ group might prove a particularly suitable option.